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CONTACTOSAKA
HEAD OFFICE

DAIWA MINAMIMORIMACHI BLDG.,
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KITA-KU,OSAKA 530-0041 JAPAN
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FAX:+81-6-6351-5664
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TOKYO
HEAD OFFICE

WORLD TRADE CENTER BLDG. 21F,
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The trademark of HARAKENZO is based on a global map including lands each of which has a size corresponding to the number of patents registered in 1991.
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Semiconductor Circuit Layout
(Mask Work) Consultation
Chief of the Semiconductor Circuit Layout Registration S.S. Kazunori TAKEDA
Head of the Tokyo Legal Division Kenjiro FUJITA
Representative of Hiroshima Office Shinji IMANO
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Semiconductor Circuit Layout (Mask Work) Consultation

 
Japanese Information Overseas Information Staff
 

Greeting

The purpose of the registration for establishment of a circuit layout right based on “The Act Concerning the Circuit Layout of Semiconductor Integrated Circuit” is to promote the stability of the circuit layout trading by protecting the right of the creator of the circuit layout (including circuitry elements and lead wires) as a Circuit Layout Right from illegal copies and thereby to contribute to the sound development of the national industry and economy.

After the registration for establishment, a circuit layout right is created. The holder of a circuit layout right shall have the exclusive right to use the circuit layout for which registration for establishment is obtained for business purposes such as manufacturing and assignment.

The registration for establishment of a circuit layout right started in 1986, and the following chart shows the statistics on the number of application since 1986 through 2006. (as of the year-end 2006)

  1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 Total
Application 432 427 462 321 283 358 233 139 119 94 58 92 9,070
Rejection 0 0 0 0 0 0 0 0 0 0 0 0 1
Withdrawal 0 0 0 1 0 0 0 0 0 0 0 0 6
Transfer 30 0 7 1 0 0 258 0 1 0 0 0 315
Inspection 23 31 15 8 0 12 7 0 2 0 21 1 468
Copy 1 5 5 3 1 1 0 0 2 11 4 0 94

The following chart shows the number of application on country-by-country basis. (as of the year-end 2006)


  1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 Total
Japan 389 371 427 288 261 336 231 136 119 94 55 92 8,233
U.S.A. 27 43 30 22 19 21 0 0 0 0 0 0 634
Netherlands 14 12 5 3 3 1 2 2 0 0 0 0 107
Germany 2 1 0 0 0 0 0 0 0 0 0 0 48
U.K. 0 0 0 0 0 0 0 0 0 0 0 0 16
Sweden 0 0 0 0 0 0 0 0 0 0 0 0 9
France 0 0 0 0 0 0 0 0 0 0 2 0 9
Korea 0 0 0 8 0 0 0 0 0 0 0 0 10
Australia 0 0 0 0 0 0 0 0 0 0 0 0 1
Switzerland 0 0 0 0 0 0 0 1 0 0 0 0 2
Finland 0 0 0 0 0 0 0 0 0 0 1 0 1
Total 432 427 462 321 283 358 233 139 119 94 58 92 9,070

Our legal department and patent technical staff will introduce you to the system of registration for establishment of a circuit layout right. We hope this could be some help for your further understanding of this system.

Chief of the Semiconductor Circuit Layout Registration S.S.
Patent and Trademark Attorney Kazunori TAKEDA

Head of the Tokyo Legal Division            
Patent and Trademark Attorney Kenjiro FUJITA

Representative of Hiroshima Office            
Patent and Trademark Attorney Shinji IMANO


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